Soft-switching voltage-edge-rate-limiting power inverter

ABSTRACT

An auxiliary resonant soft-edge pole inverter circuit is provided. The power inverter circuitry may include a first pair of capacitors in parallel with a corresponding pair of main power switching modules, each power switching module comprising a switch and a diode in parallel and sharing a common central node with the first pair of capacitors. The power inverter circuit may further include a first pair of auxiliary switches connected in series with a first pair of inductors, respectively, to generate resonant current from a DC power source, the first pair of inductors also sharing the common central node. The power inverter circuitry may further include a second pair of auxiliary switches connected in series with a second pair of capacitors, respectively, the second pair of auxiliary switches also sharing the common central node, the circuit producing an alternating current output at the common central node.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application No.62/865,292 filed Jun. 23, 2019, the entirety of which is herebyincorporated by reference.

STATEMENT REGARDING GOVERNMENT FUNDING

This invention was made with government support under DE-EE0005568awarded by the Department of Energy. The government has certain rightsin the invention.

TECHNICAL FIELD

The present application relates to DC-to-AC power inverters, and morespecifically, to soft-switching inverters.

BACKGROUND

Switch-mode DC-to-AC inverters are widely used in variable-speed motordrive systems and other applications. To increase switching frequencyand reduce switching loss, power switches have been made faster in thepast decades. The switching times of insulated-gate bipolar transistors(IGBTs) have reduced to tens of nanoseconds, while those of wide-bandgap(WBG) devices, such as Silicon Carbide and Gallium Nitride devices, havereduced to several nanoseconds.

As switches are made faster, the inverter output voltage edge rate(dv/dt) becomes larger. Various deleterious effects have beenexperienced and documented since the introduction of IGBTs. Theseproblems include overvoltages at the motor/inverter terminals,electromagnetic interference, large common-mode currents, and thefailure of motor bearings due to induced micro-arcs. To reduce theoccurrence of problems resulting from high dv/dt, some standards havebeen established that limit the dv/dr going into motor drives, amongwhich the US National Electrical Manufacturers Association (NEMA) MG1Part 31 is commonly observed in the US.

Conventional dv/dt-limiting methods include increasing the external gateresistance or Miller capacitance of the switches, and adding a dv/dtfilter between the inverter and the motor. All of these methods,especially the dv/dt filter, can effectively reduce the dv/dt but willintroduce extra losses, size and weight of the system.

Soft-switching inverters that are originally developed to reduceswitching loss can also limit the dv/dt in the circuits. They canpossibly replace the dv/dt filter which may result in reduction in totalloss and size/weight. Among various soft-switching inverter topologies,the auxiliary resonant commutated pole (ARCP) inverter and its variantsare suitable for variable-speed motor drive systems because they havefull pulse width modulation (PWM) control capabilities. The originalARCP inverter can realize zero-voltage switching (ZVS) and zero-currentswitching (ZCS) in its main and auxiliary switches, respectively.However, it has several drawbacks. First, the necessary mid-voltagepoint requires extra balancing circuits. Secondly, a boost current needsto be generated, which requires accurate current sensing and/or switchtriggering, and results in complicated control. Thirdly, thereverse-recovery current of the auxiliary diodes will induce a largevoltage across the auxiliary switches. Therefore, snubbers orvoltage-clamping circuits are required, which generate extra losses. Toeliminate these drawbacks, some variants of the ARCP were proposed overthe past decades.

One approach to improve the ARCP is to use a transformer or coupledinductor. A topology described in J. D. Herbst, F. D. Engelkemeir, andA. L. Gattozzi, “High power density and high effciency convertertopologies for electric ships,” in Proc. IEEE Electric Ship Technol.Symp. (ESTS), April 2013, pp. 360-365 uses a 1:1 transformer to create avirtual mid-voltage point, and the auxiliary switches only conduct halfof the resonant current. However, the transformer needs to be resetafter each switching cycle by extra circuits. A transformer-assistedresonant pole inverter is proposed in X. Yuan and I. Barbi, “Analysis,designing, and experimentation of a transformer-assisted pwmzero-voltage switching pole inverter,” IEEE Trans. Power Electron., vol.15, no. 1, pp. 72-82, January 2000. Its transformer has a turns ratiodifferent from one so the boost current is not required, which makescontrol simpler. The transformer current can be properly reset. However,the transformer is bulky and its leakage inductance is part of theresonant inductor which makes parameter design more challenging.

The other approach to improve the ARCP is represented by the auxiliaryresonant pole (ARP). The ARP connects the resonant inductor to the upperor lower DC bus through auxiliary switches so it does not need amid-voltage point. Due to this configuration, the boost current is notrequired, and the auxiliary switch turn-on and the main switch turn-offcan be triggered at the same time, which makes control simpler. Inaddition, the transient voltage across auxiliary switches is clamped tothe DC-bus voltage by auxiliary diodes. However, there are still somedrawbacks with the ARP inverter. The auxiliary switches have lossyhard-switched turn-off. In addition, there may be a circulating currentin the auxiliary circuits when a main switch module is conductingcontinuously, which again generates loss. A circuit proposed in W. Yu,J. S. Lai, and S. Y. Park, “An improved zero-voltage switching inverterusing two coupled magnetics in one resonant pole,” IEEE Trans. PowerElectron., vol. 25, no. 4, pp. 952-961, April 2010 uses two coupledmagnetics as resonant inductors so the circulating current can beprevented. However, the turn-off transients of the auxiliary switchesare not perfect ZCS because of the remaining magnetizing current.Therefore, improvements are needed in the field.

The active auxiliary edge resonant pole (AAERP) (see M. Nakamura, T.Yamazaki, Y. Fujii, T. Ahmed, and M. Nakaoka, “A novel prototype ofauxiliary edge resonant bridge leg link snubber-assisted soft-switchingsine-wave PWM inverter,” Elect. Eng. Jpn., vol. 155, no. 4, pp. 64-76,2006) and the double ARCP (DARCP) (see E. Chu, X. Zhang, and L. Huang,“Research on a novel modulation strategy for double auxiliary resonantcommutated pole soft-switching inverter with the shunt dead time,” IEEETrans. Power Electron., vol. 31, no. 10, pp. 6855-6869, October 2016)improve upon ARP by adding a second pair of capacitors to realize ZVSturn off in the auxiliary switches. However, the second pair ofcapacitors may not be precharged to the DC-bus voltage, so the outputdv/dt may sometimes be large.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following description and drawings, identical reference numeralshave been used, where possible, to designate identical features that arecommon to the drawings.

FIG. 1 is a schematic and timing diagram illustrating an auxiliaryresonant soft-edge pole inverter circuit according to various aspects.

FIG. 2A is a schematic and timing diagram illustrating operation of apower inverter in a diode-to-switch (D2S) commutation during timeInterval A according to various aspects.

FIG. 2B is a schematic and timing diagram illustrating operation of apower inverter in a D2S commutation during time Interval B according tovarious aspects.

FIG. 2C is a schematic and timing diagram illustrating operation of apower inverter in a D2S commutation during time Interval C according tovarious aspects.

FIG. 2D is a schematic and timing diagram illustrating operation of apower inverter in a D2S commutation during time Interval D according tovarious aspects.

FIG. 2E is a schematic and timing diagram illustrating operation of apower inverter in a D2S commutation during time Interval E according tovarious aspects.

FIG. 2F is a schematic and timing diagram illustrating operation of apower inverter in a D2S commutation during time Interval F according tovarious aspects.

FIG. 2G is a schematic and timing diagram illustrating operation of apower inverter in a D2S commutation during time Interval G according tovarious aspects.

FIG. 2H is a schematic and timing diagram illustrating operation of apower inverter in a D2S commutation during time Interval H according tovarious aspects.

FIG. 3A is a schematic and timing diagram illustrating operation of apower inverter in a switch-to-diode (S2D) commutation during timeInterval H according to various aspects.

FIG. 3B is a schematic and timing diagram illustrating operation of apower inverter in an S2D commutation during time Interval I according tovarious aspects.

FIG. 3C is a schematic and timing diagram illustrating operation of apower inverter in an S2D commutation during time Interval J according tovarious aspects.

FIG. 3D is a schematic and timing diagram illustrating operation of apower inverter in an S2D commutation during time Interval K according tovarious aspects.

FIG. 3E is a schematic and timing diagram illustrating operation of apower inverter in an S2D commutation during time Interval L according tovarious aspects.

FIG. 4 is a schematic and timing diagram illustrating operation of apower inverter circuit in a D2S commutation during time Interval C₂according to various aspects.

FIG. 5A-B are state-plane plots of ARSEP and AAERP according to variousaspects.

FIG. 6 is a schematic illustrating an auxiliary resonant soft-edge poleinverter circuit with metal-oxide-semiconductor field-effect transistors(MOSFETs) according to various aspects.

The attached drawings are for purposes of illustration and are notnecessarily to scale.

DETAILED DESCRIPTION

In the following description, some aspects will be described in termsthat would ordinarily be implemented as software programs. Those skilledin the art will readily recognize that the equivalent of such softwarecan also be constructed in hardware, firmware, or micro-code. Becausedata-manipulation algorithms and systems are well known, the presentdescription will be directed in particular to algorithms and systemsforming part of, or cooperating more directly with, systems and methodsdescribed herein. Other aspects of such algorithms and systems, andhardware or software for producing and otherwise processing the signalsinvolved therewith, not specifically shown or described herein, areselected from such systems, algorithms, components, and elements knownin the art. Given the systems and methods as described herein, softwarenot specifically shown, suggested, or described herein that is usefulfor implementation of any aspect is conventional and within the ordinaryskill in such arts.

The present disclosure provides a soft-switching circuit to control aninverter output dv/dt with less loss, size and weight than prior-artdv/dt limiting methods, while eliminating the drawbacks of prior-artsoft-switching circuits. A circuit topology is provided, referred toherein as an auxiliary resonant soft-edge pole (ARSEP) inverter thatrealizes soft-switching in all of the main and auxiliary switches andensures that the inverter dv/dt is limited by circuit parameters. Thesecond pair of resonant capacitors will always be fully pre-charged sothe inverter dv/dt can be well-controlled.

One embodiment of a single-phase ARSEP inverter is shown in FIG. 1, inwhich auxiliary circuits are illustrated using a dashed box. CapacitorsC₁ and C₂ are connected in parallel with the main switch modules S₁/D₁and S₂/D₂. Auxiliary switches S₃ and S₄ are connected in series withinductors L₁ and L₂ to generate resonant current.

It is notable that S₃ and S₄ are unidirectional to prevent circulatingcurrent. Capacitors C₃ and C₄ have two roles. When S₅ (S₆) is on, C₃(C₄) facilitates soft-switching of the main switches; when S₅ (S₆) isoff, C₃ (C₄) and D₃ (D₄) serve as the turn-off snubber of S₃ (S₄).Diodes D₅ and D₆ enable pre-charging of C₃ and C₄, which prepares themfor the next resonant process so that the dv/dt is well-controlled bycircuit parameters. Diodes D₇ and D₈ direct residue energy in L₁ and L₂back to the power source. It is assumed that C₁=C₂=C_(a), C₃=C₄=C_(b),and L₁=L₂=L. The “+” signs in FIG. 1 define the ports where positivecurrent goes into the devices.

Output Current I_(o) may be constant during commutation. Since inverteroperation is symmetric for positive and negative output current I_(o),without losing generality, the circuit operation with a positive outputcurrent (I_(o)>0) will be explained in the following subsections. Theoutput current is generally constant during the commutation because thecommutation time is relatively short.

A. Diode-to-Switch Commutation

A commutation in which the output current I_(o) commutes from a diode toa switch is called a diode-to-switch (D2S) commutation.

Interval A (t<t₀): Initially, S₂ is ON while D₂ actually conducts I_(o)(FIG. 2A). Voltages v_(C1)=E, v_(C2)=0, and v_(C3)=E due to the presenceof D₅. In order to demonstrate the basic operation of the circuit, it isassumed that C₄ is initially pre-charged, i.e., v_(C4,0)=E. Thesituation where v_(C4,0)<E will be discussed further below.

Interval B (t₀≤t<t₁): At to, a D2S commutation is commanded. Switch S₂is turned off while S₃ and S₅ are turned on (FIG. 2B). Since D₂ isconducting, S₂ is turned off with zero-voltage-zero-current switching(ZVZCS). Since i_(L1)(t₀)=0, S₃ is turned on with ZCS. Sincev_(C3)(t₀)=E, S₅ is turned on with ZVZCS. Current i_(L1) increasessubstantially linearly.

Interval C (t₁≤t<t₂): At t₁, i_(L1) increases to I_(o) whereupon D₂stops conducting and L₁ starts to resonate with C₁, C₂, and C₃ (FIG.2C). Voltage v_(o) increases while v_(C4) stays at E since S₆ is OFF.

Interval D (t₂≤t<t₃): At t₂, v_(o) reaches E and the resonance stops(FIG. 2D). Current i_(L1) supplies I_(o). Since i_(L1)>I_(o), the extracurrent circulates in the circuit shown in FIG. 2D. Based on simulationand experiment, the extra current circulates in the L₁-D₁-S₃ andL₁-S₅-D₃ loops. The current in the L₁-D₆-D₈-S₃ loop is negligiblebecause there are two diodes in this loop. Ideally, i_(L1) is constantand is actually at its peak value

$\begin{matrix}{{I_{L1p} = {\frac{E}{Z_{1}} + I_{o}}}{where}} & (1) \\{Z_{1} = \sqrt{\frac{L}{{2C_{a}} + C_{b}}}} & (2)\end{matrix}$

Interval E (t₃≤t<t₄): At 13, S₁ is turned on while S₃ and S₅ are turnedoff so it starts to charge C₃ (FIG. 2E). Since D₁ is conducting, S₁ isturned on with ZVZCS. Since v_(C3)(t₃)=0, S₃ and S₅ are turned off withZVS. The energy in L₁ at t₃ is

W _(L1)=½L ₁ I _(L1p) ²>½C _(b) E ²+½LI _(o) ²  (3)

Therefore, L₁ has enough energy to charge C₃ to E.

Interval F (t₄≤t<t₅): At t₄, C₃ is charged to E whereupon D₇ starts toconduct (FIG. 2F). The energy transferred to C₃ is ½C_(b)E², so theenergy remains in L₁ is still higher than ½LI_(o) ² according to (3).Therefore, i_(L1)(t₄)>I_(o), so D₁ still conducts current. Currenti_(L1) will decrease linearly, and the energy will flow back to the DCsource.

Interval G (t₅≤t<t₆): At t₅, i_(L1) decreases to I_(o) while D₁ stopsconducting and S₁ starts to conduct (FIG. 2G). Current i_(L1) decreaseslinearly to zero at t₆, which ends the D2S commutation.

B. Switch-to-Diode Commutation

A commutation in which the output current commutes from a switch to adiode is called a switch-to-diode (S2D) commutation.

Interval H (t₆≤t<t₇): Prior to an S2D commutation, the circuit is inInterval H where S₁ is conducting (FIG. 3A).

Interval I (t₇≤t<t₈): At t₇, an S2D commutation is commanded so S₁ isturned off while S₄ and S₆ are turned on. Inductor L₂ starts to resonatewith C₁, C₂, and C₄ (FIG. 3B). Since v_(C1)(t₇)=0, S₁ is turned off withZVS. Since i_(L2)(t₇)=0, S₄ is turned on with ZCS. Since v_(C4)(t₇)=E,S₆ is turned on with ZVZCS. Voltage v_(o) decreases and v_(C3) stays atE since S₅ is OFF.

Interval J (t₈≤t<t₉): At t₈, v_(o) decreases to zero and i_(L2) startsto circulate in the circuit (FIG. 3C). According to the simulation andexperiment, i_(L2) circulates in the L₂-S₄-D₂ and L₂-D₄-S₆ loops. Thecurrent in the L₂-S₄-D₇-D₅ loop is negligible. Ideally, i_(L2) isconstant and is at its peak value

$\begin{matrix}{I_{L2p} = {\sqrt{I_{o}^{2} + \left( \frac{E}{Z_{1}} \right)^{2}} - I_{o}}} & (4)\end{matrix}$

Interval K (t₉≤t<t₁₀): At t₉, S₂ is turned on while Sa and S₆ are turnedoff. Current i_(L2) starts to charge C₄ (FIG. 3D). Since D₂ isconducting, S₂ is turned on with ZVZCS. Since v_(C4)(t₉)=0, S₄ and S₆are turned off with ZVS. Unlike the D2S commutation, L₂ may not havesufficient energy to charge C₄ up to E. Here, it is assumed that L₂ hassufficient energy so v_(C4) reaches E.

Interval L (t₁₀≤t<t₁₁): At t₁₀, v_(C4) reaches E and D₈ starts toconduct. Current i_(L2) decreases linearly to zero at t₁₁, whichcompletes an S2D commutation.

C. Alternative Mode of Operation

According to (4), I_(L2p) decreases when I_(o) increases. The energy inL₂ in Interval J is

W _(L2)=½LI _(L2p) ²  (5)

It may be less than ½C_(b)E², especially when I_(o) is large or C_(a) ismuch smaller than C_(b). Therefore, C₄ may not be charged to E evenabsorbing all energy in L₂. In this case, Interval K ends at t′₁₀ wheni_(L2) decreases to zero. The circuit operation will then skip IntervalL and goes directly to Interval A. Then, the initial voltage of C₄ forthe next D2S commutation v_(C4,0) is less than E. In the next D2Scommutation, C₄ stays at v_(C4,0) in Interval B. Interval C willactually have two subintervals denoted by Intervals C₁ and C₂.

Interval C₁ (t₁≤t<t_(1.5)): This interval is similar to Interval C (FIG.2C) except that v_(C4) stays at v_(C4,0).

Interval C₂ (t_(1.5)≤t<t₂): At t_(1.5), v_(o) increases to v_(C4,0) andD₆ starts to conduct current (FIG. 4). Inductor L₁ starts to resonatewith C₁₋₄. When v_(o) increases to E, i_(L1) increases to its peak value

$\begin{matrix}{{I_{L\; 1p}^{\prime} = {\sqrt{{\left( \frac{E - v_{{C\; 4},0}}{Z_{3}} \right)^{2}\left( {1 - \frac{Z_{3}^{2}}{Z_{1}^{2}}} \right)} + \left( \frac{E}{Z_{1}} \right)^{2}} + I_{o}}}{where}} & (6) \\{Z_{3} = \sqrt{\frac{L}{{2C_{a}} + {2C_{b}}}}} & (7)\end{matrix}$

Since Z₃<Z₁ and I_(L1p)′>I_(L1p), according to (3), L₁ has enough energyto charge C₃ up to E, and the remaining i_(L1) is still greater thanI_(o). This interval ends at t₂ when v_(o) increases to E. Voltagev_(C4) increases to E at t₂, which prepares for the next S2Dcommutation. This pre-charging feature is not available in AAERP orDARCP, so they may result in high dv/dt.

D. Summary of Circuit Operation

The gating signals of the ARSEP inverter can be generated based on thePWM signal and a time delay t_(d), as shown in FIG. 3. The requirementon t_(d) is

$\begin{matrix}{{{t_{d} > {t_{B} + t_{C}}} = {\frac{I_{o}L}{E} + t_{C}}}{where}} & (8) \\{\frac{\pi}{2\omega_{1}} \leq t_{C} < \frac{\pi}{2\omega_{3}}} & (9) \\{\omega_{1} = \frac{1}{\sqrt{L\left( {{2C_{a}} + C_{b}} \right)}}} & (10) \\{\omega_{3} = \frac{1}{\sqrt{L\left( {{2C_{a}} + {2C_{b}}} \right)}}} & (11)\end{matrix}$

From (8), t_(d) is a function of I_(o). The first term depends oncircuit parameters, and the second term is mainly determined byallowable dv/dt. Therefore, it is possible to reduce t_(d) through theparameter design to cater to high switching frequencies.

If t_(d) is constant, all gating signals can be generated without anysensing. Then, t_(d) should be longer than the maximum possible voltagecommutation time

$\begin{matrix}{t_{c,\max} = {\left( {t_{B} + t_{C}} \right)_{\max} = {\frac{I_{p}L}{E} + \frac{\pi}{2\omega_{3}}}}} & (12)\end{matrix}$

where I_(p) is the peak output current. If I_(o) is measured by acurrent sensor, a lookup table can be used to determine the requiredt_(d). Then, the duration of Intervals D and J as well as the associatedlosses can be reduced without affecting the dv/dt performance.

The circuit operation can be represented in a more concise way using astate-plane plot as shown in FIG. 5A. The two normalized states for thestate-plane plot are defined as:

$\begin{matrix}{{\overset{¯}{i} = \frac{iZ_{1}}{E}},{\overset{¯}{v} = \frac{v}{E}}} & (13)\end{matrix}$

The moving directions of the state are indicated by arrows. From t₁ tot_(1.5), the state follows a circular arc about the center (1, Ī_(o))with a rotational speed of ω₁. Similarly, from t₇ to t₈, the statefollows another circular arc about the center (0, Ī₀) with the samespeed ω₁. If v_(C4,0)=E, from Point P, the state will keep following thesolid circular arc to Point Q. If v_(C4,0)<E, from Point P, the statefollows the dashed curve and goes to Point R.

The state-plane plot of AAERP is shown in FIG. 5B. When C₃ and C₄ arefully charged, the state follows the solid line to Point Q. However,when C₃ or C₄ is lightly charged (which is likely when I_(o) is large),the state moves from the origin to Point P and then to Point R, duringwhich high dv/dt will occur. DARCP suffers a similar problem. ARSEPsolves the problem by pre-charging C₃ (C₄) through diode D₅ (D₆) so thatdv-dt can be well controlled by circuit parameters.

E. Voltage and Current Characteristics

The peak inductor current, di/dt, and dv/dt in the ARSEP inverter can bederived as:

$\begin{matrix}{I_{L,\max} = {{\frac{E}{Z_{3}} + I_{p}} = {\left( {\frac{1}{{\overset{¯}{Z}}_{3}} + 1} \right)I_{p}}}} & (14) \\{\frac{di_{L}}{{dt}_{\max}} = \frac{E}{L}} & (15) \\{{\frac{dv_{o}}{{dt}_{\max}} = \frac{{0.8}E\omega_{1}}{\Delta{\theta_{T2D}\left( {\overset{¯}{Z}}_{1} \right)}}}{where}} & (16) \\{{\Delta{\theta_{S2D}\left( {\overset{¯}{Z}}_{1} \right)}} = {{\cos^{- 1}\frac{0.1}{\sqrt{{\overset{¯}{Z}}_{1}^{2} + 1}}} - {\cos^{- 1}\frac{0.9}{\sqrt{{\overset{¯}{Z}}_{1}^{2} + 1}}}}} & (17)\end{matrix}$

is the angle being swept when V, decreases from 0.9 to 0.1, as shown inFIG. 5A, because dv/dt defined by the NEMA MG-1 standard is the averagevoltage-change rate when the voltage changes between 10% and 90%. Thenormalized impedance is defined as

$\begin{matrix}{\overset{¯}{Z} = \frac{I_{p}Z}{E}} & (18)\end{matrix}$

F. Example Table 1—ARSEP Inverter Design Specification (Example)

Item Value DC-bus voltage, E 200 V Peak output current, I_(p) 20 AMaximum voltage edge rate, dv/dt_(limit) 200 V/μs Maximum current edgerate, di/dt_(limit) 50 A/μs Maximum inductor current, I_(L, limit) 50 ASwitching frequency, f_(sw) 10 kHz Maximum commutation time 5 μs

By way of example, given the specifications in Table 1, an ARSEPinverter may be designed as follows. Referring to (14)

$\begin{matrix}{{{\overset{¯}{Z}}_{3} > \frac{I_{p}}{I_{L,{limit}} - I_{p}}} = {{0.6}7}} & (19)\end{matrix}$

It is selected that Z ₃=1 to limit the maximum inductor current. Basedon (2) and (7), it can be concluded that Z₁>Z₃, so it is selected that Z₁=1.1. Subsequently, according to (16) and (17)

$\begin{matrix}{{\Delta\theta_{S2D}} = {{0.5}83\mspace{14mu}{rad}}} & (20) \\{\omega_{1} = {\frac{\frac{dv}{{dt}_{limit}}\Delta\theta_{S2D}}{0.8E} = {{0.7}29\mspace{14mu}{{rad}/{\mu s}}}}} & (21)\end{matrix}$

Based on Z ₁, Z ₃, and ω₁, the values of the resonant components arecalculated to be L=15 μH, C_(a)=50 nF, and C_(b)=25 nF. In order tomaximize the benefit of soft switching, C_(b) should be large enough sothat S₃ and S₄ are over-snubbed. With this design, according to (12) and(14)-(16), t_(cmax)=3.9 μs, I_(Lmax)=40 A, di_(L)/dt_(max)=13.3 A/μs,and dv_(o)/dt_(max)=200 V/μs, which satisfy NEMA standards.

FIG. 6 illustrates an example of the circuit. The switches may beinclude metal-oxide-semiconductor field-effect transistors (MOSFETs) (asshown in FIG. 6), an insulated-gate bipolar junction transistor (IGBT),or other suitable transistor. When the switches labelled S₃ and S₄ areMOSFET devices, there are diodes in series with the MOSFET “switch”(labeled D₉ and D₁₀ in FIG. 6), since the unidirectional switches S₃ andS₄ should conduct current in one direction only.

The presently disclosed ARSEP circuit may be implemented to controlpower inverters in hybrid and electric vehicles, aircraft actuators,ship propulsion, and grid integration of renewable energy sources, orother applications.

In various aspects and examples, the auxiliary resonant soft-edge poleinverter circuit may include a first pair of capacitors (C₁ and C₂) inparallel with a corresponding pair of main power switching modules, eachpower switching module comprising a switch (S₁/S₂) and a diode (D₁/D₂)in parallel and sharing a common central node with the first pair ofcapacitors.

The auxiliary resonant soft-edge pole inverter circuit may furtherinclude a first pair of auxiliary switches (S₃ and S₄) connected inseries with a first pair of inductors (L₁ and L₂) to generate resonantcurrent from a DC power source (E), the first pair of inductors alsosharing the common central node.

The auxiliary resonant soft-edge pole inverter circuit may furtherinclude a second pair of auxiliary switches (S₅ and S₆) connected inseries with a second pair of capacitors (C₃ and C₄). The second pair ofauxiliary switches (S₅ and S₆) also sharing the common central node, thecircuit producing an alternating current output at the common centralnode.

The auxiliary resonant soft-edge pole inverter circuit may furtherinclude a second pair of diodes (D₃ and D₄) connected between the secondpair of auxiliary switches (S₅ and S₆) and the inductors (L₁ and L₂).

The auxiliary resonant soft-edge pole inverter circuit may furtherinclude a third pair of diodes (D₅ and D₆) connected in parallel withthe second set of auxiliary switches (S₅ and S₆) and sharing the commoncentral node.

The auxiliary resonant soft-edge pole inverter circuit may furtherinclude a fourth pair of diodes (D₇ and D₉) connected between the secondpair of auxiliary switches (S₃ and S₄) and the DC power source (E).

The auxiliary resonant soft-edge pole inverter circuit may furtherinclude a fifth pair of diodes (D₉ and D₁₀) respectively connected inseries with the second pair of auxiliary switches (S₃ and S₄).

In various aspects and examples, the power inverter may include aplurality of capacitors comprising a first capacitor C₁, a secondcapacitor C₂, a third capacitor C₃, and a fourth capacitor C₄. The powerinverter may further include a plurality of switches. The switches mayinclude a first switch S₁, a second switch S₂, a third switch S₃, afourth switch S₄, a fifth switch S₅, and a sixth switch S₆. The powerinverter may include a plurality of inductors. The inductors may includea first inductor L₁ and a second inductor L₂. The power inverter mayfurther include a plurality of diodes comprising a first diode D₁ and asecond diode D₂.

The first switch S₁ may be connected in parallel with the firstcapacitor C₁ and the first diode D₁. The second switch S₂ may beconnected in parallel with a second capacitor C₂ and a second diode D₂.

The third switch S₃ may be connected in series with the first inductorL₁. The fourth switch S₄ may be connected in series with the secondinductor L₂.

The fifth switch S₅ may be connected in series with the third capacitorC₃ and the sixth switch S₆ may be connected in series with the fourthcapacitor C₄.

The first switch S₁, the second switch S₂, the first diode D₁, thesecond diode D₂, the first capacitor C₁, the second capacitor C₂, thefirst inductor L₁, the second inductor L₂, and the fifth switch S₅ andthe sixth switch S₆ may share a common node.

In some examples, the diodes further comprise third diode D₃ and fourthdiode D₄. The third diode D₃ may be connected between the third switchS₃ and the first inductor L₁. The fourth diode D₄ may be connectedbetween the second inductor L₂ and the fourth switch S₄.

In some examples, the diodes may further include a fifth diode D₅ andsixth diode D₆. The fifth diode D₅ may be connected in parallel with thefifth switch S₅ and the sixth diode D₆ may be connected in parallel withthe sixth switch S₆. Further, the fifth diode D₅ and the sixth diode D₆may both connect to the common node.

In some examples, the diodes may include a seventh diode D₇ and an eightdiode D₈. The seventh diode D₇ may be connected between the fourthswitch S₄ and a DC power source E. The eight diode D₈ may be connectedbetween the third switch S₃ and the DC power source E.

In some examples, the third switch S₃ and the fourth switch S₄ mayinclude MOSFETs. In such examples, the diodes may further include adiode D₉ and a diode D₁₀. The diode D₉ may be connected in series withthe third switch in S₃. The diode D₁₀ may be connected in series withthe fourth switch in S₄. Alternatively or in addition, the powerinverter may include switch circuitry (identified as 602 and 604 in FIG.6). The switch circuitry may include a series connection of a diode anda MOSFET.

The invention is inclusive of combinations of the aspects describedherein. References to “a particular aspect” and the like refer tofeatures that are present in at least one aspect of the invention.Separate references to “an aspect” (or “embodiment”) or “particularaspects” or the like do not necessarily refer to the same aspect oraspects; however, such aspects are not mutually exclusive, unless soindicated or as are readily apparent to one of skill in the art. The useof singular or plural in referring to “method” or “methods” and the likeis not limiting. The word “or” is used in this disclosure in anon-exclusive sense, unless otherwise explicitly noted.

The invention has been described in detail with particular reference tocertain preferred aspects thereof, but it will be understood thatvariations, combinations, and modifications can be effected by a personof ordinary skill in the art within the spirit and scope of theinvention.

1. An auxiliary resonant soft-edge pole inverter circuit, comprising: afirst pair of capacitors in parallel with a corresponding pair of mainpower switching modules, each power switching module comprising a switchand a diode in parallel and sharing a common central node with the firstpair of capacitors; a first pair of auxiliary switches connected inseries with a first pair of inductors, respectively, to generateresonant current from a DC power source, the first pair of inductorsalso sharing the common central node; and a second pair of auxiliaryswitches connected in series with a second pair of capacitors,respectively, the second pair of auxiliary switches also sharing thecommon central node, the circuit producing an alternating current outputat the common central node.
 2. The circuit of claim 1, furthercomprising a second pair of diodes respectively connected in series withthe first pair of auxiliary switches.
 3. The circuit of claim 1, furthercomprising a second pair of diodes connected between the second pair ofauxiliary switches and the inductors, respectively.
 4. The circuit ofclaim 3, further comprising a third pair of diodes connected in parallelwith the second set of auxiliary switches and sharing the common centralnode.
 5. The circuit of claim 4, further comprising a fourth pair ofdiodes connected between the second pair of auxiliary switches and theDC power source.
 6. The circuit of claim 1, wherein at least one of theswitches comprises insulated-gate bipolar transistor.
 7. The circuit ofclaim 1, wherein at least one of the switches comprise ametal-oxide-semiconductor field-effect transistor (MOSFET).
 8. A powerinverter circuit, comprising: a plurality of capacitors comprising afirst capacitor, a second capacitor, a third capacitor, and a fourthcapacitor; a plurality of switches comprising a first switch, a secondswitch, a third switch, a fourth switch, a fifth switch, and a sixthswitch; a plurality of inductors comprising a first inductor and asecond inductor; and a plurality of diodes comprising a first diode, asecond diode, wherein the first switch is connected in parallel with thefirst capacitor and the first diode, and the second switch is connectedin parallel with a second capacitor and a second diode, wherein thethird switch is connected in series with the first inductor and thefourth switch is connected in series with the second inductor, whereinthe fifth switch is connected in series with the third capacitor and thesixth switch is connected in series with the fourth capacitor, andwherein the first and second switch, the first and second diode, thefirst and second capacitor, the first and second inductor, and the fifthand sixth switch share a common node.
 9. The power inverter of claim 8,wherein the third and fourth switches comprise metal-oxide-semiconductorfield-effect switches (MOSFET), and the diodes further comprise thirdand fourth diode, the third diode connected in series with the thirdswitch, and the fourth diode connected in series with the fourth switch.10. The power inverter of claim 8, wherein the diodes further comprisethird and fourth diode, the third diode is between the third switch andthe first inductor, and the fourth diode is connected between the secondinductor and the fourth switch.
 11. The power inverter of claim 10,wherein the diodes further comprise a fifth and sixth diode, wherein thefifth diode is connected in parallel with the fifth switch and the sixthdiode connected in parallel with the sixth switch, the fifth and sixthdiode both connected to the common node.
 12. The power inverter of claim11, further comprising a seventh and eighth diode, wherein the seventhdiode is connected between the fourth switch and a DC power source, andthe eighth diode is connected between the third switch and the DC powersource.
 13. The power inverter of claim 8, wherein at least one of theswitches comprises insulated-gate bipolar switches.
 14. The powerinverter of claim 8, wherein at least one of the switches comprise ametal-oxide-semiconductor field-effect transistor (MOSFET).